void CDead63701::AddCycles(int n)			//add cycles to cycle counter
{
//u32 t,b,i;

Cycle += n;				//add cycle to the cycle counter
/*
t = Counter + n;		//interment free running counter
if(t >= 0x10000)		//check for interrupt
	{
	TCSR |= F_TCSR_TOI;
	if(((CC & F_IRQ) == 0) && (TCSR & F_TCSR_ETOI))
		{DO_TOI;}
	}
for(i=Counter,b=Cycle;b<(Cycle+n);b++,i++)	//check output compare register
	{
	if(OutputCompare == i)							//if match found, generate oci
		{
		TCSR |= F_TCSR_OCI;
		if(((CC & F_IRQ) == 0) && (TCSR & F_TCSR_EOCI))
			{DO_OCI;}
		}
	if(OutputCompare2 == i)							//if match found, generate oci2
		{
		TCSR2 |= F_TCSR2_OCI;
		if(((CC & F_IRQ) == 0) && (TCSR2 & F_TCSR2_EOCI))
			{DO_OCI;}
		}
	}
Counter = (u16)t;		//save value back to counter
*/
}

u8 CDead63701::ReadInternalReg(u32 addr)
{
switch(addr)
	{
	default:
		message("reading internal register $%02X\n",addr);
		break;
	case 0x00:		//port 1 data direction reg
		return(Port1DDR);
	case 0x01:		//port 2 data direction reg
		return(Port2DDR);
	case 0x02:		//port 1 data
		return((Read(0x100) & (Port1DDR ^ 0xFF)) | (Port1Data & Port1DDR));
	case 0x03:		//port 2 data
		return((Read(0x101) & (Port2DDR ^ 0xFF)) | (Port2Data & Port2DDR));
	case 0x08:		//tcsr
		return(TCSR);
	case 0x14:		//ram control reg
		message("reading ram control reg = $%02X\n",RAMCtrlReg);
		return(RAMCtrlReg);
	}
return(0);
}

#define TCSRChanged()	\
	Interrupts2 = (TCSR & (TCSR << 3)) & (F_TCSR_ICI | F_TCSR_OCI | F_TCSR_TOI);

#define SetTimeNext()	\
	if((CompareData - Counter) < (TimeOver - Counter))	\
		TimeNext = CompareData;	\
	else							\
		TimeNext = TimeOver;

#define CounterChanged()	\
	CompareData &= 0xFFFF;	\
	if((CompareData & 0xFFFF) >= (Counter & 0xFFFF))	\
		CompareData |= Counter & 0xFFFF0000;	\
	else							\
		CompareData |= (Counter + 1) & 0xFFFF0000;	\
	SetTimeNext();

#define IncrementCounter(n)		\
	Counter += n;						\
	if(Counter > TimeNext)			\
		{									\
		if(Counter >= CompareData)	\
			{								\
			CompareData += 0x10000;	\
			TCSR |= INT_OCI;			\
			TCSRInfo |= INT_OCI;		\
			TCSRChanged();				\
			if(((CC & F_IRQ) == 0) && (TCSR & F_TCSR_EOCI))	\
				{DO_OCI;}				\
			}								\
		if(Counter >= TimeOver)		\
			{								\
			TimeOver += 0x10000;		\
			TCSR |= INT_TOI;			\
			TCSRInfo |= INT_TOI;		\
			TCSRChanged();				\
			if(((CC & F_IRQ) == 0) && (TCSR & F_TCSR_ETOI))	\
				{DO_TOI;}				\
			}								\
		SetTimeNext();					\
		}

void CDead63701::WriteInternalReg(u32 addr,u8 data)
{
switch(addr)
	{
	default:
		message("writing internal register $%02X = $%02X\n",addr,data);
		break;
	case 0x00:		//port 1 data direction reg
		if(Port1DDR != data)
			{
			Port1DDR = data;
			if(Port1DDR == 0xFF)
				Write(0x100,Port1Data);
			else
				Write(0x100,(Port1Data & Port1DDR) | (Read(0x100) & (Port1DDR ^ 0xFF)));
			}
		break;
	case 0x01:		//port 2 data direction reg
		if(Port2DDR != data)
			{
			Port2DDR = data;
			if(Port2DDR == 0xFF)
				Write(0x101,Port2Data);
			else
				Write(0x101,(Port2Data & Port1DDR) | (Read(0x101) & (Port2DDR ^ 0xFF)));
			}
		break;
	case 0x02:		//port 1 data
		Port1Data = data;
		if(Port1DDR == 0xFF)
			Write(0x100,Port1Data);
		else
			Write(0x100,(Port1Data & Port1DDR) | (Read(0x100) & (Port1DDR ^ 0xFF)));
		break;
	case 0x03:		//port 2 data
		Port2Data = data;
		if(Port2DDR == 0xFF)
			Write(0x101,Port2Data);
		else
			Write(0x101,(Port2Data & Port2DDR) | (Read(0x101) & (Port2DDR ^ 0xFF)));
		break;
	case 0x08:
		message("writing tcsr = $%02X\n",data);
		TCSR = data;
		TCSRInfo &= data;
		TCSRChanged();
		if((CC & F_IRQ) == 0)
			{
			CHECK_ICI;
			CHECK_OCI;
			CHECK_TOI;
			}
		break;
	case 0x09:
		message("writing counter high = $%02X\n",data);
		Latch = data;
		Counter = 0xFFF8;
		CounterChanged();
		break;
	case 0x0A:
		message("writing counter low = $%02X\n",data);
		Counter = (Latch << 8) | data;
		CounterChanged();
		break;
	case 0x0B:			//compare high byte
		message("writing compare high = $%02X\n",data);
		if((u8)(CompareData >> 8) != data)
			{
			CompareData &= ~0xFF00;
			CompareData |= data << 8;
			CounterChanged();
			}
		break;
	case 0x0C:			//compare low byte
		message("writing compare low = $%02X\n",data);
		if((u8)(CompareData & 0xFF) != data)
			{
			CompareData &= ~0xFF;
			CompareData |= data;
			CounterChanged();
			}
		break;
	case 0x14:		//ram control reg
		RAMCtrlReg = data;
		message("writing ram control reg = $%02X\n",RAMCtrlReg);
		break;
	case 0x17:		//?
		break;
	}
}
